In the field of semiconductor memory devices, in addition to volatile memories such as a DRAM and an SRAM, various types of non-volatile semiconductor memory devices including a flash memory, an MRAM, and an FeRAM have been developed. In the volatile memories, when a power supply is disconnected, information is lost. The flash memory utilizes a floating gate. These non-volatile semiconductor memory devices can store information even if a power supply has been disconnected. The phase-change memory among these semiconductor memory devices is drawing attention because the time necessary for erasing a write in the phase-change memory is short. The phase-change memory is a memory of which a material capable of being electrically programmed to assume an amorphous state or a crystalline state is used for a part of a memory cell. In this memory, it is determined whether the material is in the amorphous state or in the crystalline state by a resistance value of the memory cell, thereby reading data.
Assume that memory cell data before rewritten and external write data from an outside for rewriting the memory cell data are identical in the above-mentioned phase-change memory. In this case, a resistance value can be made stable by not performing writing. Though not limited to the phase-change memory alone, when unnecessary writing is not performed, the life of the memory cell can be extended, and a program current can be reduced. The following proposals have been made from this point of view.
Patent Document 1 describes a phase-change memory including phase-change memory elements. In each phase-change memory element, a high-resistance state and a low-resistance state can be electrically programmed. Then, a current state of the memory element is read. When the current state is different from a state to be programmed, the programming is performed.
Patent Document 2 describes a phase-change memory in which a storage state of the phase-change memory is read from a rising waveform of a write pulse. When the storage state coincides with information to be written, rewrite processing is stopped.
FIG. 11 and FIGS. 22 to 24 of Patent Document 3 respectively disclose circuits where control is performed to stop writing on a memory cell of which data has been changed from “0” to “1” (of which the threshold has been increased). This control is performed during a repeated operation of writing caused by electron injection (FN tunneling) and verification in NAND-EEPROMs.
FIGS. 5 and 6 of Patent Document 4 describe a phase-change memory in which a read data latch, a write data latch, and a transfer switch are provided. The read data latch holds data read from a cell and write data. The write data latch holds the data written into the cell. The transfer switch controls transfer from the read data latch to the write data latch. When the contents of the read data latch and the write data latch do not match, writing is performed using the write data latch.    [Patent Document 1]
JP Patent Kohyou Publication No. JP-P2003-502791A, which corresponds to US Patent Publication No. U.S. Pat. No. 6,075,719A.    [Patent Document 2]
International Publication No. WO2005/041204 A1    [Patent Document 3]
JP Patent Kokai Publication No. JP-P2000-215684A    [Patent Document 4]
JP Patent Kokai Publication No. JP-P2008-159178A, which correspond to US Patent Application Publication US2008/151656A1.    [Patent Document 5]
JP Patent Kokai Publication No. JP-P2003-100085A, which correspond to US Patent Application Publication US2003/067013A1.    [Patent Document 6]
JP Patent Kokai Publication No. JP-P2005-100617A, which correspond to US Patent Application Publication US2005/068804A1.    [Patent Document 7]
JP Patent Kokai Publication No. JP-P2004-362761A, which correspond to US Patent Application Publication US2004/246804A1.